3d Pdn Design And Analysis

Use Altium Designer comes with PDN Analyzer to PDN instance simulation analysis of power supply planes, super classic!

tags: PCB design Analog circuit design

Article catalog

1 PDN Analysis and Application Series --- Altium Designer PDN Analyze Introduction
- 1.1 PDN Analysis Floor
2 PDN Analysis and Application Series 2 - Example Analysis 1: Simple 5V Power Network
- 2.1 Simple 5V power distribution
- 2.2 Visualization Power Analysis
- 2.3 Complex load model representation
3 PDN Analysis and Application Series Three --- Example Analysis 2: Series Power Network Connection
- 3.1 Sedentially expand power network
- 3.2 Containing Voltage Adjustment Model (VRM)
4 PDN Analysis and Application Series 4 - Example Analysis 3: Limit Analysis of Multi - network Simulation
- 4.1 Analysis of simulation failure
- 4.2 Identify power integrity key points
- 4.3 Data detection and image capture
- 4.4 voltage profile
- 4.5 Analysis Report

Introduction to power integrity, you can see this article
Deep understanding power integrity

1 PDN Analysis and Application Series - Overview of Altium Designer PDN Analyze

The PDN Analyzer Interface As the panel, it can be conveniently called by Altium Designer, which can be placed in any convenient location on the workspace or other screen. The upper part of the PDN analyzer GUI is mainly interactive, and the lower half of the currently selected power network provides access to the analysis option, display setting, and results data. Simultaneous multi-network simulation can analyze the entire PCB design of DC (DC) power supply integrity as a hierarchy or a separate power supply network. The display and results are displayed in the panel below. The following is a definition of some important terms.

Network: Electrical connection between two or more element pins in design.

Source: Element or circuit powered by the rest of the circuit.

Load: Elements or circuits that require power to work.

Online: This is a collection of power and ground networks. In order to simulate, at least there is a source and one load.

Line Raid: A collection of power networks in the network (for example, a network power line rail or ground track). Whether it is or negative, both the power line or negative is generally placed on the top of the network.

Config: One or more sets of networks that are similarities simultaneously.

Profile: Saved configuration file, extension ".pdna".

Simultaneous multi-network simulation: Collaborative simulation of all networks including online interactions.

Batch simulation: the order of the two or more configurations in the simulation tree.

1.1 PDN Analysis Floor

The options summarized below briefly describes the settings you will see on the PDN analyzer interface. If some elements do not display properly, adjust the size of the interface panel. Fields of gray background cannot be edited, additional information is required to activate editing operations. Fields of thicker or clear fonts can be edited as needed.

FILE (file) - contains basic file operations and layout controls.

New Simulation - Create a new network simulation and can be configured as needed.

Open - Allows the previously saved PDN analyzer configuration.

Save - Allows the PDN analyzer configuration.

Save as (Save As) - Allows the use of a specific name to save the PDN analyzer configuration.

Explore - Opens the Windows Explorer project source file location.

Explore Samples - Opens the Windows Explorer file location.

Compact Layout - You can modify the panel layout for docking.

DC NETS (DC Network) - Opens the PDN Analyzer DC Network Identification dialog box.

Analyze - Only the analysis of the lower left corner can only be activated after providing all the required parameters.

2 PDN Analysis and Application Series 2 - Example Analysis 1: Simple 5V Power Network

Pre-equation DC network identification

When the PDN analyzer is initially opened for the PCB, it will attempt to identify all DC power networks from the design according to the public power network naming method. The correct DC network identification is very important for obtaining the most accurate simulation results. The master DC network has been identified in the sample item to simplify the process.

Note: Click the network entry listed in the dialog to cross the network in the PCB layout. Other networks can be identified at any time by selecting the DC Nets button in the main panel interface.

Simulation settings

Analysis results, especially the degree of IR losses in the plate shape, also depends on the Copper Conductivity and Via Wall Thickness, depending on the Copper Copper conductivity and the via wall thickness. Any changes to the simulation settings need to be analyzed and re-effective.

Right-click the current analysis setting name, then select "Settings" from the context menu.

Metal conductivity definition

The metallic Conductivity section provides detailed information and setting of the electrical conductivity value (the ability of the metal conduction current and the reciprocal of the electrical conductivity; 1 / r). You can select or modify the base conductivity, resistivity, base temperature, temperature compensation (analog temperature), and / or the percentage of the resistivity of the degree of resistivity to reflect the design of the circuit board structure properties of the design.

Note: The displayed SIM Conductivity diagram represents the final conductivity value after all the temperature compensation parameters considering the defined infrastructure. Sim Resistivity represents the countdown of Sim Conductivity.

Overhead

"VIA Wall Thickness" value specifies the thickness of all via walls (plated through-Hole Metal) in the design simulation analysis. This setting can significantly affect the power network DC loss due to the inherent resistance represented by Thin-Walled (Plated). However, when the number, size and thickness are sufficient, the via (or through holes) do not impede the DC performance of the design, and will display the current density similar to the power trace connected thereto - and the voltage loss between its connection points can be can be ignored.

In terms of simulation, the via size and wall thickness effectively define the amount of conductive material represented by the via, and thus its resistance / conductivity is defined. The simulation assumes that the via diameter represents the inner hole size of the finished product, and the thickness of the via hole will increase the via diameter. Therefore: finished inner hole size Finished Hole Size = Hole Size - (2x Via Wall Thickness).

LIMITS settings

Define specific current and current density restrictions, will trigger violations at the time of exceeding. The current density of the surface / internal layer and the via is limited to the "Limits Tab" tab of the Settings dialog box. The specified current density limit will be automatically applied to completed analysis. Any network containing violations will be displayed in red dashed outline.

You can use the formula in IPC-2221 to determine current limit from the defined trace width and via. The PDN Analyzer determines the appropriate current limit for all via size, which ranges from the defined Hole Size 1 to Hole Size 2. The new design does not set the default limit when analyzing. The hyperthermia is currently made.

2.1 Simple 5V power distribution

This example demonstrates the basics of power integrity simulation using a simple power network and its current load.

It is configured as a Spiritlevel-SL1 reference project that is loaded as an LCD display in the design project. The power supply is 5V allocation and its ground loop. In this case, the 5V power source is considered a simple voltage source and does not include the network it is connected (e.g., by switch S1).

2.2 Visualization Power Analysis

You can view the simulation results in a graphical way in the Altium Designer PCB editor.

In this case, a view of the selected network path voltage drop, from 5V source from TP1 to the LCD1 element color gradient, corresponding to the voltage scale displayed at the bottom of the view. It shows voltage

Percentage (PER RAIL option under Color Scale), or text voltage range (Displayed option).

PDN Analyzer provides a variety of interactive display options to determine how to display the analysis results in a graphical mode in the Altium Designer PCB editor. In addition to displaying the options for displaying Color Scale, graphics can also switch between 2D and 3D rendering, which provides valuable analysis results between layers that cannot be seen between the via and 2D.

2.3 Complex load model representation

More loads can be added to the network as needed, and the power analysis is re-run to evaluate the results. For example, you can add a small load current (15mA) in your design and re-run analysis. The PDN analyzer allows the load-bearing device pin connection definition. Define Pin Connections allows multiple load models to be created for a single component device, and the current consumption between the pins is different.

The LCD device in the sample project demonstrates this situation, where the pin 15 (LED +) is connected to the display backlight power supply, and the 5V connection of the pin 2 (VDD) is internal logic power supply - in fact, the pin 15 will More current is consumed than pin 2. The LCD1 is represented as two load models to improve the accuracy of the power analysis: each 5V pin is a load current associated with it. When adding as a single PDNA load model, two pins of LCD1 are specified (by default) as 5V load connections, and PDN analysis is equipped with an average LCD1 load current between these pins.

R15 in the sample project is also used as a load, similar.

3 PDN analysis and application series three - instance analysis 2: series power network connection

Example Analysis 2 shows how to make overall analysis of a range of connected networks while considering the parameters of the series elements they are interconnected. In addition, there is an overview of how to add a voltage regulator model "Voltage Regulator Models (VRM), which can also act as the electrical and logical links between the networks, and how to develop a complete hierarchy of the design power network.

This example is a network modeling of the PWR_IN to 5V of the Spiritlevel-SL1 reference item and includes 3.3V (VCCO) and 1.8V (VCCINT) VRM to create a complete power network structure.

3.1 Sedentially expand power network

3.2 Containing Voltage Adjustment Model (VRM)

The PDN analyzer provides an active voltage regulator model "Voltage Regulator Models (VRM)" that can be inserted between the voltage input and output of the network. When added to the PDNA power network, they are manneited as a load on the voltage input network, and it behaves as a power supply on the voltage output network. The VRM model option includes linear "linear", switch mode "SwitchMode" and remote sensing switch mode voltage regulator "Remote-Sensing SwitchMode Voltage Regulators". Voltage Adjustrator Model (VRM) is very powerful in the PDN analyzer because they can define in multiple components to simulate the function of the entire regulator circuit.

Spiritlevel-SL1 Reference item uses a linear regulator to generate 3.3V (VCCO) and 1.8V (VCCINT) power. When the VCCO regulator (U3) is added to the PDNA simulation network, it is represented as the source of load on the 5V input network and the source of the 3.3V network.

4 PDN Analysis and Application Series Four - Example Analysis 3: Limit Analysis of Multi-Network Simulation

In this example, we will load the completed profile and view the special analysis of the PDN Analyzer. After the analysis is completed, the lower half of the PDN analysis panel will enable multiple viewing and reporting functions. The upper half of the panel, the red or green state icon indicates the limit check state in the power distribution network.

Select File >> Open to navigate to the ConfigFiles_2.0 folder, then select an existing all_pwr_nominal.pdna configuration file.

Select all_pwr_nominal network settings to load an existing PDN configuration.

Use the "Analyze" button to start analysis.

In the three power channels in this design, the 1.8V (VCCINT) channel has an extreme check failure, such as the v-line red contour, the VcCint symbol, and the red status icon on the left side of the VCCint network listed in the upper left corner. The restriction check fault will be analyzed later and resolve the restriction check.

The contents of the results pane "Results Pane" are described below:

Initial results - Visual Tab

Display Filters: Displays the filter. Used to control the voltage level or current density in the actual PCB layout. The current direction arrow can be enabled to indicate current flow in the layout.

Highlight Peak Values: Highlight the peak. Provides a function of positioning, highlighting and scaling and scaling a peak (such as the lowest voltage, the highest current density). It also provides the ability to move to the next (minimum / maximum) value.

Voltage contour: Voltage profile. Enable tags in a specific voltage or percentage point in the layout.

Net and Layer: Allows the PDN Analyzer results of a specific network and layers.

Views: view. Allows the PDN Analyzer result to be displayed as 2D or 3D. The Overlay option provides a visual context display of non-PDN-specific objects. The Clear button can delete the display of all PDN analyzers in the PCB layout.

Color Scale: Color. The color gradient representation of the control voltage or current density information.

4.1 Analysis of simulation failure

4.2 Identify power integrity key points

PDN Analyzer provides comprehensive graphics and data information, which can be used to assess power integrity of PCB designs and troubleshoot them. Take the above example, the analysis of the top GND (TOP Layer GND) network path indicates the position of the current density hotspot, such as the maximum scale reading 39.1 A / mm2 and the current density gradient proximity to the via. The location of the problem area is not very obvious, but it can be positioned using the "Highlight Peak Values" and "Current Directional Arrows" function.

4.3 Data detection and image capture

In addition to the visual display of PDNA analysis graphics and zoom in the PCB editor, the probe tool also helps detect the analysis results of the design layout specific point. The probe tool can record and compare the voltage or current density data of the designation point in the design layout. The multi-functionality of this tool provides a method of accurately determining analysis data results in any network or layer. The differential comparison of the current density on the VCCINT network will be described below.

4.4 voltage profile

Voltage Contour enables you to find the best probably location of the layout. This feature can overlay the broken line voltage profile line through the display layer in the PCB editor graph to indicate the critical voltage conversion point in the board layout. You can specify a plurality of outlines and display it as a percentage or text representation of the network voltage drop. There are multiple outline combinations at a specific percentage, and the slider option can be used to continuously adjust the position of the conversion point.

4.5 Analysis Report

In order to store the result of the power integrity analysis to further check or distribute to the relevant person, PDN Analyzer provides data and document reporting functions. The Report feature generates a very comprehensive HTML-based document, including graphics and data of the current analysis and board design itself. You can also add a picture of the voltage outline line to the report.

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